1. Field of the Invention
This invention relates to the field of integrated circuit design and testing. More particularly, the present invention relates to the tuning of integrated circuit parameters after fabrication.
2. Description of the Related Art
The typical design and fabrication of an integrated circuit (IC) involves the following steps. The desired functional behavior of the IC is first specified. Next, the various functional blocks needed to implement the desired functions are selected and strategically placed on the die of the IC. The output signal responses to anticipated input signal conditions of the functional blocks are defined. A processing technology suitable for the intended operating clock frequency and the circuit complexity of the IC is selected. The functional blocks are then implemented using circuit elements fabricated using the selected process technology. Finally, the circuit is fabricated and tested for proper functioning in response to the anticipated input signal conditions.
With the ever increasing complexity of large scale integrated (LSI) circuits, especially very large scale integrated (VLSI) circuits, the production of a completely bug-free and robust IC in a single design and fabrication cycle is an elusive if not impossible task. In addition, because the complex IC processing technology is aggravated by shrinking line geometries and interconnect resolutions, slight variations in dopant levels or imperfections in circuit elements can cause a functional block to behave in a manner substantially different than intended. As a result, the unintended process variations can multiply the detrimental effects of any design problems and increase the deviation between the intended functional behavior and actual behavior of the IC.
While conventional computer aided design (CAD) tools such as circuit simulators are useful for predicting the behavior of ICs prior to fabrication, these CAD tools depend on mathematical models for approximating the underlying behavior of the circuit elements. Further, the achievable accuracy and resulting dependability of the IC simulations are limited by the available computer resource and the IC complexity. Hence, the generation of complete and accurate simulations of an entire VLSI circuit under all possible input signal and operating conditions is highly improbable. As a result, CAD tools have limited usefulness for detecting and correcting design errors.
Although conventional techniques for correcting some types of design and processing problems after fabrication do exist, these techniques only provide a partial solution because they provide limited relief and have major inherent disadvantages. Examples of conventional techniques include laser trimming of IC elements such as resistors, and the incorporation of redundant memory elements selectable by fusible links.
Laser trimming involves using a narrowly focused laser beam to remove by vaporizing a portion of an element or creating an electrical short across a portion of an element. In either case, the laser beam necessitates access to the IC itself and the resulting changes are irreversible, i.e., permanent in nature. In addition, the laser beam may cause damage to the surrounding crystalline structure of the IC and also creates a considerable amount of debris which can contaminate surrounding circuit elements, unless an extra area of the IC is dedicated for the creation of buffer zones.
Redundant circuits are generally cost effective only in circuits with a large number of predominantly repetitive functional blocks, e.g., memory arrays. For example, redundant memory circuits enables a designer to internally replace a faulty memory circuit with one of the redundant memory circuits after fabrication thereby partially mitigating the effects of design and/or processing problems. However, the location of the replacement redundant memory circuit typically results in a longer signal path with the accompanying increase in parasitic resistance and capacitance. U.S. Pat. No. 5,204,836, Reed, discloses a redundant memory storage structure implemented using duplicate arrays connected to laser zappable fuses.
Hence there is a need for VLSI circuits with target portion(s) which can be changeably tuned after fabrication to correct any circuit design problem and/or compensate for unintended parametric variations arising from the process steps.